In digital electronics, there are systems that require a digital clock output signal to be frequency-locked to a reference clock source, and further require the phase alignment of the output clock to be occasionally adjusted without otherwise impacting the frequency synchronization with the reference. Additionally, other digital systems require two or more clock signals to be frequency-locked to a common reference. A clock and frame-sync pair is a common example as shown in FIG. 1. In such a system scenarios can arise where one of these clocks requires a one-time phase adjustment without otherwise impacting the frequency synchronization of either clock signal. After the clock and frame-sync have frequency-locked to the input reference, the frame-sync may also need to be phase aligned with a second signal, such as a time-of-day (ToD) seconds indicator.
In many applications, such as the ones described above, industry standards or other practical reasons exist that require the phase alignment to be glitchless, i.e. occurring without a sudden phase jump. Making an adjustment glitchless may involve limiting the size of the phase movement per clock cycle. Additionally, there may be requirements that limit when the phase adjustments are allowed. For instance, in the previous example, the phase adjustment is typically not desired during the high portion of the signal. The exact parameters defining the allowable rate and position of a glitchless phase adjustment are application specific, so it is desirable that the phase adjustment mechanism be flexible in this regard.
A variety of methods have been used to address these requirements. One such method, shown in FIG. 2, involves momentarily adjusting the Frequency Control input to a Numerically Controlled Oscillator (NCO), Digitally Controlled Oscillator (DCO), or a Voltage Controlled Oscillator (VCO). These devices allow the frequency of an output clock to be adjusted by changing a control input to the device. To perform a phase adjustment, the frequency is momentarily increased or decreased until the desired phase movement has been achieved. The disadvantages of this approach are that it cannot instantaneously apply an arbitrarily large phase step, the phase step cannot be easily timed within the high or the low portion of the clock, and it requires time sensitive control via the controller logic.
Another method involves adjusting the phase error as seen by the input to a standard PLL. During the steady-state locked condition of a PLL, the input phase error to the PLL (the difference between the input reference and the fed back signal from the PLL output) is at or near zero. To accomplish a phase adjustment, a constant phase offset (in the amount of the desired phase step) can be summed into the PLL's phase error input. This will cause the PLL to lock to the input reference, shifted by the desired phase adjustment. As shown in FIG. 3, there are three points in the input side of the PLL where the phase may be added: 1) as an offset to the input reference phase, 2) as an offset to the PLL feedback phase, and 3) as an offset to the output of the phase detector. This method is easier to control as it less time sensitive on the controller, but still cannot be an instantaneous adjustment, as the output movement is limited by the PLL's loop bandwidth. Additionally, in the case of a PLL synchronizing multiple output clocks, this solution precludes the ability to shift one of the outputs independently of the others.
The last mechanism, shown in FIG. 4, involves summing a phase offset directly into the output. In this method, a Digital PLL (DPLL) and some number of clock synthesizers are driven from the same master clock reference (which can be distinct from the input reference clock). The DPLL's output frequency and phase information are used to program the clock synthesizers to generate the final derived clock that is synchronized with the DPLL's input reference. To accomplish a phase adjustment, a one-time phase offset is summed into the desired synthesizer's phase input. While this method is fast and requires little controller logic support, it can introduce large, uncontrolled, instantaneous phase steps into the output signal.